1. Field of the Invention
The present invention relates to a method of fabricating a split gate flash memory device.
2. Discussion of the Related Art
Generally, a flash memory device, which is a non-volatile memory device capable of maintaining information stored in its memory cell without a power supply, is mounted on a circuit board to enable high-speed electrical erasures.
Flash memory technology keeps evolving in a manner of modifying cell structures variously. The various cells can be classified into a stacked gate cell, a split gate cell, and the like.
In the stacked gate cell, a floating gate and a control gate are sequentially stacked. Yet, the stacked gate cell has a problem of over-erasing. The over-erasing takes place when the floating gate is over-discharged. A threshold voltage of the over-discharged cell shows a negative value. Even if the cell is not selected, i.e., even if a read voltage is not applied to the control gate, a current flow takes place. To overcome the over-erase problem, a split gate cell structure has been proposed.
A method of fabricating a split gate flash memory device according to a related art is explained as follows.
FIGS. 1A to 1D are cross-sectional diagrams for explaining a method of fabricating a split gate flash memory device according to a related art.
Referring to FIG. 1A, an ONO (oxide-nitride-oxide) layer 102, a first conductor layer, an oxide layer 104, and a nitride layer 105 are sequentially stacked on a semiconductor substrate 101. The nitride layer 105, the oxide layer 104, and the conductor layer are patterned to form a first gate pattern 103. Annealing is carried out on the substrate 101 to grow thermal oxide layers 106 on left and right sidewalls of the first gate pattern 103.
Referring to FIG. 1B, an exposed portion of the ONO layer 102 failing to be covered with the first gate pattern 103 is etched away. A gate oxide layer 107 is grown on an exposed surface of the substrate by thermal oxidation. A second conductor layer 108 is then deposited over the substrate including the first gate pattern 103.
Referring to FIG. 1C, the second conductor layer 108 is selectively patterned to remain on one side of the first gate pattern 103. Hence, a second gate pattern 108a is formed on one side of the first gate pattern 103 to complete a split gate constructed with the first and second gate patterns 103 and 108a. A thermal oxide layer 109 is formed on a surface of the second gate pattern 108a. Ion implantation is lightly carried out on the substrate 101 to form lightly doped regions n− for an LDD (lightly doped drain) structure in the substrate below both sides of the split gate, respectively.
Referring to FIG. 1D, a spacer 110 is formed on a sidewall of the second gate pattern 108a. Ion implantation is heavily carried out on the substrate to form heavily doped regions n+ for a source and drain in the substrate adjacent to the lightly doped regions, respectively. A pair of symmetrical split gates is formed in a memory cell area by the related art method. Since the first gate pattern, the oxide layer and the nitride layer are stacked on a pair of prescribed portions of the substrate in depositing the second conductor layer for the second gate patterns of the split gates, a recess is provided between a pair of split gate areas due to the step difference of the first gate pattern, oxide layer and nitride layer.
In forming the second gate patterns by patterning the second conductor layer, a portion of the second conductor layer between a pair of the split gate areas is incompletely etched whereas the other portion of the split gate areas is completely removed.
Specifically, a polymer is generated as an etch residue when the second conductor layer is selectively removed by wet etch. The polymer is accumulated between the first gate patterns and prevents an etchant gas from being sufficiently supplied to the space between a pair of the split gates. This prevents completion of the etching process.
As a result, stringers 120 in FIG. 3 are generated in the space between a pair of the split gate areas. The space between a pair of the split gate areas corresponds to a portion where a contact hole for connection to an upper line will be formed. Hence, the stringers degrade electrical characteristics such as contact resistance and the like.
In the related art method, the thickness of the insulating layer stacked on the first gate pattern is decreased to suppress the generation of the stringers. However, if the thickness of the insulating layer stacked on the first gate pattern is decreased, parasitic capacitance between the first and second gate patterns is increased.